In our previous newsletter, we presented a digital filter implemented with  floating point math in C. This time we present a filter using fixed point math in VHDL. A code snippet for a first-order IIR filter form is expressed as follows: 

PROCESS (resetn, lpfclk) BEGIN
   IF (resetn = '0') THEN
      w1 <= (others => '0');  y     <= (others => '0');
      x  <= (others => '0');  lpfout <= (others => '0');
   ELSIF (lpfclk'EVENT and lpfclk = '1') THEN
      w1 <= w0;       y      <= rightsum(31 DOWNTO 16);
      x  <= lpfin(15 downto 0); lpfout <= slpfout;
   END IF;
END PROCESS;

-- low pass filter --
A1W1 <= a1 * w1; -- use the negative of computed a1 for pos sum
-- make x value Q16 for Q16 addition, sign extend
xQ16 <= X"0000" & x & X"0000" when x(15)='0'
   else X"FFFF" & x & X"0000";  
leftsum <= xQ16 + A1W1; -- leftsum Q16 result
w0 <= leftsum(43 downto 16); 
rightsum <= w0 * b0;  --rightsum Q16 result
slpfout <= y;   -- output

-- low pass filter --

  

Check the code example link later this week for the full VHDL example code. Follow the filter design calculations and frequency response link to determine coefficient values. 

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