By Daniel Casner  

Building ever-smarter technology, we perpetually require more sensors to collect increasing amounts of data for our decision-making machines. Power and bandwidth constraints require signals from individual sensors to be aggregated, fused and condensed locally by sensor hubs before being passed to a local application processor or transmitted to the cloud. FPGAs are often used for sensor hubs because they handle multiple parallel data paths in real time extremely well and can be very low power. ADC parallel interfaces and simple serial shift register interfaces are straightforward to implement in FPGA logic. However, interfacing FPGAs with more complex serial devices--which are becoming more common as analog and digital circuitry are integrated--or serializing collected data is often less straightforward. Typically, serial interfaces are implemented in FPGA fabric as a state machine where a set of registers represents the state of the serial interface, and each clock cycle, logic executes depending on the inputs and state registers. For anything but the most trivial serial interface, the HDL code for these state machines quickly balloons into a forest of parallel if-elseif-else trees that are difficult to understand or maintain and take large amounts of FPGA fabric to implement. Iterating the behavior of these state machines requires recompiling the HDL and reprogramming the FPGA for each change which is frustratingly time consuming. Custom soft cores offer an alternate solution. Continue Reading