Bringing Up A New FabOver the past nine months, Tekmos has been qualifying a new fab for our 0.35u production. There are a lot of steps involved with that that I will review here.
Fortunately, there are a lot of similarities in the available 0.35u process. A well designed part that works in one process will likely work the same way when manufactured in another fabs 0.35u process. The challenge is in the conversion from one process to another.
The conversion starts with the layout rules. The rules from both fabs must be compared and differences identified. In our case, the rules had one major difference: the gate length for 5 volt transistors increased from 0.5u to 0.6u. An increase in length of 500 atoms may not seem like a lot, but it caused a lot of problems. In a gate array architecture, the key design parameter is the routing grid that is used for interconnect. There are many variables that influence the grid, but one of the main ones is the center to center spacing of two contacts with a gate between them. When this changed, the entire routing grid changed, and that meant that we could not reuse our existing layouts.
Instead, we had to create a new technology based on the new process. As with all new technologies, we study the layout rules, and create DRC checks to verify that our new layouts are compliant with those rules. We check our work by creating a structure that contains each layout rule with a good and bad case. Then we run our DRC checks on that structure to validate the checks themselves.
Next we create the "block" that contains the transistors that we use to build everything else. A block typically consists of three pairs of transistors. Why three? This is a tradeoff between efficiency in building a logic gate, and the waste if a given gate doesn't use all of the resources. As with most things in life, the optimum is "e", or 2.71. Since we must use whole transistors, we have a choice between 2 and 3 pairs. We chose 3 pairs. Most companies use 3 pairs. Some use 2 pairs, and a few use 4 pairs.
Once we have a block, we build up our library of logic gates. For the most part, our library is unchanged between the different technologies that we use, and this time was no exception. Using a common library prevents mistakes in creating new technologies, and makes it easier for designers to use the libraries. The new library is subjected to LVS and DRC checks before it is added to the place and route library.
We also use the block to build up gate arrays. In our new 0.35u process, we have created gate arrays with 127K gates (176 pads) and 270K gates (256 pads). We will create at least two more, smaller gate array sizes in this technology. Read more...
