An FPGA conversion consists of creating an ASIC from the same design files that were used to make an FPGA. Customers do this to either replace an FPGA that has been discontinued, or as a cost reduction for a product that has increased in volume. The main tradeoff in an FPGA conversion is the expense of the NRE against a lower unit cost. This number breaks even with a volume of about 1000 units. For obsolete FPGAs, the cost of the NRE has to be contrasted against the other options of a system redesign or the availability of parts on the gray market.
Tekmos asks several questions before doing an FPGA conversion. How big is the design? How fast is it? How much RAM does it contain? How many pins does the design use? What type of package is required? Does it contain someone else's IP? Are there simulations? There are reasons behind these questions.
How big is the design?
This question may also be phrased as "What is the utilization?" Both questions yield the design size. The design size determines the size of the
ASIC necessary to implement it, and that determines the cost. The size also roughly corresponds with the amount of engineering work that we will have to do during the conversion. And that has an impact on the NRE charges.
How fast is it?
This is our way of determining the process technology that I will need to implement the ASIC in. FPGAs have been technology drivers, and are always pushing the wafer fabrication limits. Fortunately, an ASIC can be 2 to 3 generations behind an FPGA, and still provide the same performance. This is because a gate is inherently faster than the CLBs used inside of the FPGA for logic functions. Also, many customers do not use the FPGA anywhere near its speed capability. If we can use an older technology, we may substantially reduce both the NRE and unit price.
How much RAM does it contain?
How many pins does the design use?
What type of packages are required?
Does the design contain someone else's IP?
Are there simulations?
Implementation
to
learn the answers to these questions.
