What's JTAG test?

Joint Test Action Group (JTAG)

is the common name for what was later standarized as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture:

a. TDI (Test Data In)

b. TDO (Test Data Out)

c. TCK (Test Clock)

d. TMS (Test Mode Select)

e. TRST (Test Reset) optional.

Application of JTAG for CPLD/FPGA is allowing device programmer hardware to transfer data into internal non-volatile device memory (CPLDs). Some device programmers serve a double purpose for programming as well as debugging the device. In the case of FPGAs, volatile memory devices can also be programmed via the JTAG port normally during development work. In addition, newer parts, for instance Xilinx Virtex-5, have internal monitoring capability accessible via the JTAG port.

What testing WE can do?

a. Check the JTAG ID CODE, all CPLD/FPGA have a JTAG ID CODE.

b. Check the Part Number, can read the part number from CPLD/FPGA via JTAG.

c. Functional testing, can check the LUT, CLB, Memory, PLL, IO pins.