Custom Silicon Solutions, Inc. Newsletter
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November/December 2012
In This Issue
 
 

CSS555 &  

CSS555  Demo Kit Video

 

If you are a regular reader of our Newsletters, you may well be aware of the CSS555 Timer IC and the CSS555 Demo Kit. However, there is never enough space in a Newsletter to explain the features of the Timer IC and details of how to use the Demo Kit. So, we put together a YouTube video that will help you in this regard. We encourage you to take a look at the video and let us know what you think at Info@CustomSiliconSolutions.com.   Thanks!

 

DIP & SOIC
The CSS555C 8P DIP
&
CSS555C 8P SOIC Package

Demo Kit Graphical Interface
The Demo Kit
 Graphical User Interface 

 

 

The CSS555 Timer IC and the CSS555 Evaluation Kit are both available at Jameco Electronics. You may also download specifications for all of the CSS555 products from the CSS website, Standard Product page. 

 

 

 


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CSS Memberships: 

 

Global Semiconductor Alliance

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CSS Certifications:

 

ISO 9001:2008 Certified

ISO 9001 

 

ITAR Compliant: Registration Code M24941

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Central Contractor Registered (CCR): CAGE Code 5F3G6

 

Qmed Qualified Supplier 

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Visit us at

   

www.CustomSiliconSolutions.com

or call us at

 

949-797-9220

 

Custom Silicon Solutions, Inc.

17951 Sky Park Circle

Suite F

Irvine, CA 92614    

 

Greetings!

Welcome to the November/December edition of the CSS Newsletter.  We hope you find these articles informative and helpful in your work.

Custom Silicon Solutions (CSS) provides a true Turn-Key Solution to meet your Mixed Signal ASIC needs - from Development through Production.  Our mission is to develop an ASIC that meets your requirement at the lowest possible price and with a minimum of assistance from your technical staff.  Please visit us at  www.CustomSiliconSolutions.com for more information or send an inquiry to  Info@CustomSiliconSolutions.com.

Keith Shelton
CEO
CSS History in Non-Volatile Memory Development

 

CSS employees have a long history in the development and use of non-volatile memory. Frank Bohac and I began our non-volatile memory work in the late 70's at the Hughes Semiconductor in Newport Beach, California. Initially, we worked with Dr. Eli Harari (co-founder of SanDisk) in the Hughes Research Center. There, Eli established the practicality of applying Fowler-Nordheim electron tunneling principles to the fabrication of Floating-Gate EEPROMs.  From the Hughes Research Center we moved to the Hughes Microelectronic Division, also in Newport Beach. There, the Floating-Gate EEPROM technology was further developed to a production capable level. This required both the development of a robust fabrication process in CMOS and the development of CMOS EEPROMs designs.

Hughes EEPROM Dev Poster  

EEPROM Development at the  

Hughes Research Center

(Poster at the Computer History Museum  

in Mountain View, California)

 

An 8K bit EEPROM design was used as the vehicle to develop a robust fabrication process and to provide data to characterize the new Floating-Gate EEPROMs. Both the process development and the EEPROM design development were significant projects. Initially, the process yield (of 8K EEPROMs) was extremely low. However, with help from Hughes process engineers (especially Bruce Paynter), the process yield was increased to a level adequate for production. Next, it was determined that due to the fundamental properties of Fowler-Nordheim tunneling (charge trapping in the tunnel oxide) it was necessary to provide some replacement of worn-out memory cells via the EEPROM design. Thus we added redundant memory cells to the 8K EEPROM which could replace these failed cells. This principle of using EEPROM design to replace worn-out cells still exist today, even in more advanced EEPROM technologies.

 

In addition to the EEPROM at Hughes, we also developed the NOVRAM (a volatile RAM with a Non-volatile memory back-up) and a Non-volatile Latch circuit (a latch that is powered-on to a programmed state).   We have found that the Non-volatile Latch (NV Latch) is an especially useful circuit in Mixed-Signal ASIC designs. In these designs, the NV Latch is often used to store the setting used to trim analog functions or to store configuration settings. For these types of applications, it is required that the circuit powers-on to a defined state and these NV Latch circuits provide this capability. Many support circuits were also developed at Hughes, including the "on-chip pumper" circuit used to generate the programming voltage necessary to program the non-volatile memories.

 

A much more in-depth review of the CSS employee history in NV memory may be found on the CSS Blog, October 2012.

 

As you may have guessed, Frank and I moved from Hughes to Custom Silicon Solutions and continued to work with non-volatile memory (NVM). At CSS we specialize in applying NVM to our custom ASIC designs. Approximately 80% of our custom ASICs use NVM for storage of analog trimming, configuration settings, serial numbers and any other information our customers may request. If you have an interest in a Mixed-Signal ASIC or are in need of NVM IP, please contact us. We will be pleased to provide a free estimate for both development and production costs. You may also contact Mike McDaid, our Director of Sales, for more information or to initiate a quote by calling 949-797-9220.

 

 

 

 

Recent Customer Testimonial

    

"After several ASIC projects with CSS,
I'm impressed with their professionalism and support in completing projects on time
and with full performance."