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Low-Power Design
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Welcome to Low-Power Design, your engineering portal into the world of green/low-power design. We create, aggregate and deliver the latest design news and articles to help power the green revolution.
Check out our many sections:
And our informative, opinionated blogs:
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| Greetings! |
March was Verification Month at Low-Power Design--at least it turned out that way. We serialized two chapters of the Verification Methodology Manual for Low Power by Synopsys, Renasas and ARM and carried a feature article on formal verification by Jasper Design Automation--all of which are linked in below. We focus on design issues, and verification is one issue that requires at least as much time as the original design process. We'll be spending more time on it going forward.
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John Donovan
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 Designing With ARM--The Wrap-Up
Last week I co-chaired an EE Times virtual conference Designing with ARM: Engineering an Optimal ARM-Based System along with Rich Nass. This was my first experience with the format, and I went into it skeptical but with an open mind. Is this an effective way to convey information? Can it attract and hold an engineering audience's attention? Is this the future of trade shows, or will it have the lifespan of a fruit fly? During the show I lost my skepticism and gained some perspective. These things definitely work. More...
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Brian Fuller
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Baby StepsThe low-power wireless world is looking eagerly toward the connected home as the next big thing for systems, semiconductor and software. There's no doubt that this is the right place to be, but the approach has been all wrong. Saving the world, one dryer at a time More... |
Steve Leibson
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 Intel releases low-power, 40Gbyte SSD for $125
Now it's a trend. Last week, I wrote about the sub-$100, 2.5-inch, 32Gbyte SSD from OCZ. Now Intel makes low-cost SSDs a trend with the introduction of a $125 (when ordering 1000), 2.5-inch, 40Gbyte, "value" edition of its industry-leading X25 SSD, as reported by Computerworld's Lucas Mearian. Intel's X25-V SSD provides 25% more storage for about an eighth of the active power and about a quarter of the standby power. More...
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ISLPED 2010
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Formal Verification for Challenging Low-Power Designs
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 Designers using advanced energy-efficient techniques increase the complexity of their designs. These techniques are defined at the architectural level and have a strong impact throughout the design process. Complexity induced by multi-power domain chips and advanced low-power techniques make verification a difficult task. For all these techniques, verification is becoming the biggest bottleneck. More... |
Verification Methodology for Low Power--Part 1: Testbench Structure and Components
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 In the following pages we focus on the formulation of a testbench architecture for a multi-voltage design: especially on the methodology of migrating from a non-multivoltage environment. The primary objective of the testbench is to have the infrastructure provide effective and comprehensive testing of the multi-voltage feature set. In the process of setting up and/or migrating to a multi-voltage test setup, many issues such coding practices, modeling of various elements, file formats and others enter the picture and we will discuss these in detail. More... |
Verification Methodology for Low Power-Part 2: Multi-Voltage Testbench Architecture
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| As can be expected, the impact of power management can be felt on how code is written as well, both for the DUT and testbench. This section contains coding issues and guidelines for low power designs. These are usually encountered when migrating either existing code or coding rules to low-power designs. They involve both testbench and DUT code. More... |
Verification Methodology for Low Power-Part 3: Static Verification
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This chapter takes a detailed look at both static and dynamic verification. We cover static verification first as part of the flow and move onto dynamic verification. While an immense amount of preparation and infrastructure is needed for dynamic verification, in power managed designs, a good amount of static verification is needed to make sure that bugs that can be detected without the effort of running vectors. So, the question is, what exactly are the goals of verifying power management? More... |
Verification Methodology for Low Power-Part 4: Dynamic Verification
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| The first objective of dynamic verification is to exercise the power state table. Assuming that static verification yields a clean result, we can assume that in a steady multi-voltage state, there are no further obvious electrically hazardous conditions. Corner cases may well exist that need to be uncovered by dynamic verification. However, before we get there we have some basic functionality to verify. More... |
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That's a brief look at what we have to offer--and we're adding more every day. Please check back with us regularly to get the latest news, tips and techniques for implementing green/low-power designs.
Sincerely,
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