The Basics of Serial Data Compliance & Validation Measurements 

High-speed serial bus architectures are the new norm in today's high-performance designs. While parallel bus standards are undergoing some changes, serial buses

are established across multiple markets - computers, cell phones, entertainment systems, and others - and offer performance advantages, lower cost, and fewer traces in circuit and board designs and layouts.

You might already have experience with first- and second generation serial bus standards, like 2.5 Gb/s PCI Express® (PCIe) and 3 Gb/s Serial ATA (SATA). Engineers are now looking at the requirements in designing to third-generation specifications, including PCI Express 3.0 (8 Gb/s), that are still evolving in working groups. Serial buses continue to advance with faster edge rates and a narrower unit interval (UI), creating unique, exacting demands on your design, compliance testing, and debug processes. Standards have reached speeds at which you need to be ready for RF analog characteristics and transmission line effects that have a far bigger impact on the design than in the past.

In this primer, we look at the compliance requirements of serial standards, with focus on the issues of next generation standards. After introducing the characteristicsof several key standards, we'll look at the issues you face, including basic tests, and what you need to consider during the compliance testing and debug phases. We'lladdress five main areas: connecting to the device under test (DUT), generating accurate test patterns, testing receivers, acquiring data, and analyzing it.

Get Keithley's NEW Device Characterization E-Guide Here! 

Laser diode modules (LDMs) and Vertical Cavity Surface Emitting Lasers (VCSELs) are the primary components used in optical communications, spectroscopy, and a host of other optoelectronic applications. As the demand for these applications grows, so does the need for more efficient LDM and VCSEL test methods. With both device types there are many value-added manufacturing steps, each one adding cost to the finished assembly. The most common subset of DC characteristics can be measured with a light-current-voltage (LIV) test sweep. This fast and inexpensive test identifies failed assemblies early in the production process, so expensive non-DC domain testing is more cost-effective when conducted on the remaining higher yield compo nents.

This application note details a few cost-effective DC test systems that provide the high throughput required in today's opto production environments.

Get a FREE Test Coverage Analysis! 

ASTER Technologies is offering a FREE board level post-layout test coverage analysis report that will represent the overall test coverage provided by a combination of test/inspection systems used for testing a product. All we would need is your layout file (like FabMaster FATF file, the CAMCAD CCZ file, ODB++ file) that is used for the test program generation and the test coverages files from your different testers (AOI, AXI, ICT, FP and/or BSCAN).

In return DVTest will provide a HTML report that shows the percentage of devices fully tested, the percentage of devices partially tested and the percentage of devices NOT tested. Each device can be expanded to show individual information by pin; signal name; the type of test and whether each pin is tested, based on the same PPVS criteria that is used within the TestWay tool.

Testway Express is built around the powerful QuadView, layout and schematic viewer from Aster Technologies, allowing users to visualize coverage at both device and pin level for any combination of test/inspection machines within the production line after test program debug, such as:  

Agilent Technologies: 3070, 5DX,SJ10, SJ50; Teradyne: Z1800, Spectrum, GR228x; Aeroflex: 42xx; TRI: AOI, ICT; Takaya: APT800, APT900; SPEA: 3030, 4040; Omron; Orbotech; VI Technology; VISCOM; Saki; Acculogic; Asset; Corelis; Goepel; JTAG Technologies and XJTAG. Contact Us Today for your FREE Test Coverage Analysis